Analog to digital converters (ADCs) are well known circuits that generate a digital codeword representing an analog signal. As with many electronic circuits, power consumption is an important design element in ADCs. Accordingly, charge redistributed ADCs are preferable in many circuit applications because they generally require low power. Often, charge redistributed ADCs include an array of binary weighted capacitors in which charge is captured from an input voltage. Each capacitor corresponds to a binary bit position of the digital codeword, and each capacitor is weighted according to the capacitor's corresponding binary bit position. For example, the capacitor that corresponds to the most significant bit may have largest capacitance in the array while the capacitor that corresponds to the least significant bit may have the smallest capacitance in the array. However, in noise dominated ADCs the number and size of the capacitors correlate to the noise particularly in high resolution ADCs because the noise in ADCs varies as the square root of the overall capacitance (noise a (1/√Cap)).
Charge redistributed ADCs operate by comparing various thresholds on a bitwise basis to convert the input analog voltage to a digital codeword. During the bitwise test, the ADC will perform bit trials for each of the bit positions. One plate of each capacitor must be charged and discharged for its corresponding bit trial requiring a large amount of power. Consequently, large capacitors require large switch devices to perform the bit trials. The large switch devices also require a large amount power and have long settling times. There is a need in the art for charge redistributed ADCs that consume less power and operate faster.